The present invention relates to a semiconductor memory device; more particularly, to a circuit for an internal power voltage of the semiconductor memory device.
The semiconductor memory device includes a data storage area, a peripheral area and an I/O area. The data storage area is provided with a plurality of unit cells, each storing one data. The peripheral area is provided with circuits for efficiently accessing data stored in the unit cells. For example, there is a sense amplifier for sensing and amplifying data from a unit cell. There are also transmitting circuits for reading or writing operations. A transmitting circuit for a reading operation transmits data from a unit cell to an I/O pad in order to output the data to an external device. A transmitting circuit for a writing operation transmits data from an I/O pad to a unit cell to thereby input the data to inside of the semiconductor memory device. The I/O area is provided with a data I/O circuit and an address input circuit. The data I/O circuit is used for performing data input and output between the semiconductor memory device and an external device. The address input circuit transmits addresses input from the exterior to the peripheral area. In particular, the data I/O circuit is provided with a data output driver having higher driving ability than other internal circuits so as to efficiently output the data. The driving ability refers to an ability to generate a voltage stably.
A Dynamic Random Access Memory (DRAM), in general, has a unit cell provided with a MOS transistor and a capacitor. In order to store more data in a given area, the MOS transistor is designed smaller. Meanwhile, MOS transistors constituting the circuits in the peripheral area are designed for transmitting data faster. Accordingly, for efficient operation, different levels of internal power voltages are supplied to the data storage area and the peripheral area. Generally, the internal power voltage supplied to the data storage area is called a core voltage.
A semiconductor memory device such as a DRAM uses a capacitor for data storage. It is required that the data stored in the capacitor be refreshed regularly. Over time, the capacitor loses a charge corresponding to the data. Before the charge stored in the capacitor of the unit cell falls below predetermined amount, the semiconductor memory device operates to compensate for the lost amount of charge. This process is called a refresh operation.
The refresh operation supplies a charge to each capacitor constituting each unit cell included in the data storage area so as to thereby maintain the original charge corresponding to the original data before the loss of charge. Circuits related to data input or output in the peripheral area do not perform any actual operation during the refresh operation. Accordingly, the semiconductor memory device reduces the level of an internal power voltage for circuits irrelevant to the refresh operation, in order to decrease power consumption during the period of the refresh operation.
During normal operation when the data input or output is performed, the semiconductor memory device provides an external supply voltage to internal circuits, relevant to data input/output, in the peripheral area. Meanwhile, during the refresh operation, the semiconductor memory device provides a core voltage lower than the supply voltage to the above internal circuits. The core voltage provided to the data storage area is lower than an internal power voltage generally provided to the peripheral area. The internal power voltage for the peripheral area is generated based on the external supply voltage. That is, during the refresh operation, the semiconductor memory device provides a part of the peripheral area with the core voltage instead of the internal power voltage for the normal operation, in order to decrease power consumption.
The semiconductor memory device supplies the external supply voltage as an internal power voltage to circuits in the I/O area. Because a part of peripheral area is provided with the core voltage lower than the supply voltage during the refresh operation, malfunction can be caused in links between the peripheral and the I/O areas. Among the part of the peripheral area, data transmitting circuits are not related to the refresh operation and are connected to the I/O area. Due to a voltage difference between the data transmitting circuits and the I/O area, a leakage current can be caused. The core voltage having a lower voltage level than the supply voltage is provided to the data transmitting circuits in the refresh operation, in order to decrease the power consumption. However, this can cause other unnecessary power consumption by making current leak out.